Integrated circuit (IC) designers often desire to know whether an IC package layout design that houses various intellectual property (IP) blocks therein may function properly as designed or intended so that these IP blocks function as designed or intended. In conventional approaches, IC designers are not aware of information such as how to design an IC package, given a die design for an IP block. IC designers may also find the information about the stack-up to be used in the IC package lacking and may not know how to interconnect the pins of the IP block to the outer periphery of the IC package layout design. Moreover, IC designers may also lack sufficient information to determine an appropriate number of power planes to be used in the IC package layout design. The information about the wire widths and/or spacing values as well as a via library that an IC package layout design need to accommodate may not be available for the IC package layout designers. Furthermore, IC package layout designers often do not have sufficient information to determine the optimal number of layers (e.g., signal layer(s), Vcc layer, GND layer, etc.) required for an IC package layout.
The unavailability of design related information may be due to the concerns of the IP block owners in protecting their interests in these IP blocks. The unavailability of design related information such as the information presented above may impede the utilization, sales, or acceptance rate of IP blocks. Oftentimes, an IP block with insufficient information for an IC package layout designer to properly design the IC package therefor leads to unnecessary development effort and/or cost due to the unavailability of some of the information listed above.
From the IC designers' perspective, an IC design needs to design an IC package such that the IC package properly accommodates the IC design therein. Nonetheless, IC designers are often given the pin count of the IP block design to be included in the IC design and the connectivity of the IP block design to the rest of the IC design. IC designers are often, however, not familiar with IC package layout designs, even for their own IC designs. IC package layout designers, on the other hand, typically start with IC package stack-up on a trial-and-error basis which often leads to non-optimal development or even sub-optimal identification of the number of IC package layers to layout the IC package layout design. For example, IC package layout designers often overuse layers to interconnect the IC package layout design and the IC design by using a trial routing process to reach a fully routed IC package layout design.
To exacerbate the complexity and issues, thermal analyses for IC package layout designs are often performed late in an IC package layout design cycle through post-route analyses or actual measurements on a manufactured IC package. These post-layout thermal analyses may lead to drastic changes to the IC package layout design or even re-layout for the new stack-up or a re-spin.